1. Technical Field
The present invention relates to integrated circuit test and characterization, and more particularly to a method and apparatus for probing a wafer.
2. Discussion of Related Art
Test and analysis of integrated circuits at wafer level may use different degrees of electrical, mechanical, thermal and optical stimulus and response, depending on the application. Electrical powering and communication with the device under test (e.g., a chip(s) disposed on the wafer) is usually provided by a tester and power supplies through an electrical prober with a probe card or separate probes applied to the frontside of the wafer on which the transistors and interconnects have been fabricated. The electrical probing force on the frontside of the wafer is typically countered by force on the backside of the wafer from a contact element.
In the current state of the art, the contact element is typically a metallic disc or wafer chuck that is approximately the same diameter as the wafer to be tested. The purpose of the chuck is to hold the wafer in place for probing, provide sufficient mechanical stability so as to prevent undesired motion of the device under test when electrical contacts and their associated forces are engaged, and to provide a thermal environment for the device under test (e.g., cooling). The wafer is placed with the substrate (or backside) facing the chuck, and the circuit side (or frontside) of the wafer is presented to an electrical probing system to permit power and input-output (I/O) signals to be connected to the device under test. The force applied to the frontside of the wafer can be as much as 250 lbs. per square inch, or more. Heat dissipation and non-ambient temperature testing may be implemented using the chuck or contact element to control the device temperature. From the thermal point of view, a large wafer-sized chuck may contain nonuniform thermal contact or coolant flow across the wafer, leading to hot spots.
The nominal thickness of a semiconductor wafer is around 0.775 mm, however, in some applications the wafer can be thinned to as little as 0.010 mm (10 microns). Although these thin wafers are typically attached to a thicker handler wafer, they can be extremely fragile, and internal stress can lead to fractures and device failure. If the wafer is laterally fixed (e.g., by applying a vacuum to one side) during the application of a force such as electrical probing, internal stress may be generated at points at which a gap exists between the chuck and wafer, or by relative thermal expansion between the wafer and the chuck.
For circuit testing and analysis, optical interaction with the circuits is often required. Opaque interconnect metallization limits and often prevents frontside microscopy of the transistors, and as a result, backside microscopy through the wafer is usually required. For this reason, transparent contact elements, such as a glass plate larger than the wafer, are commercially available to allow optical interaction with the circuits. However, contact elements like the glass plate are applicable only in low force and low power dissipation applications, and are thus not suitable for testing modern microprocessors. Furthermore, current high force and high power chucks, which are suitable for testing modern microprocessors, are opaque to light transmission, thus preventing optical interaction.
Many circuit testing and analysis applications require the resolving and light-gathering power of subsurface solid immersion microscopy, which is also termed numerical aperture increasing lens microscopy. In subsurface solid immersion microscopy of circuits through the wafer, photons must tunnel across the gap that exists in practice between the lens and wafer due to mechanical mismatch, thus intimate contact is necessary. Currently available solid immersion lenses (SIL) are applied by a spring-loaded mechanism to the device under test, which must be rigidly mounted in order to avoid surface damage. A SIL typically has either a convex surface or a raised surface which makes contact with the wafer only over a very small area, which is insufficient to provide a counterforce for electrical probing. In the prior art of SIL microscopy, the chip or module as well as the SIL are considered to be rigid or inelastic. Furthermore, because chips mounted on modules generally cannot be made optically flat over a substantial area, it is typically viewed as both unnecessary and undesirable for a SIL to have a large surface area. As a result, the SIL is typically small, having a diameter of only a few millimeters. Because of the size of the SIL, the optical field of view (FOV) is small (e.g., 0.05 mm in diameter) and the SIL cannot provide a counter-force on the chip or module.
Optical probing of integrated circuits is mainly done after the wafer is diced into chips and placed on modular packages (modules). However, not all devices (e.g. kerf structures) are packaged, and are thus unavailable to optical probing at the module level. In addition, in order to package an IC chip, surface preparations and other processing steps are often required which interfere with the optical properties of the chip, and certain ideal properties of a silicon wafer (e.g. flatness) are lost upon mounting in the module. As a result, it is desirable to optically probe silicon wafers prior to packaging, and to do this optical probing in conjunction with wafer electrical testing, which minimizes overall test time.
For the foregoing reasons, there is a need for an apparatus for probing wafers of varying thickness that allows electrical, mechanical, thermal and optical control while also reducing or eliminating the likelihood of causing damage to the wafer.